Development of photothermal reflectance method for evaluating thermal contact resistance in SiP-mounted semiconductor devices (Three-dimensional heat conduction model for micro-scale sample configuration)

Y. Otsubo1, Y. Taguchi2 and Y. Nagasaka2

1School of Integrated Design Engineering, Keio University, Japan
2Department of System Design Engineering, Keio University, Japan

Keywords: thermal contact resistance
property: photothermal effect, periodic heating, thermoreflectance
material: Au-bump

Recently, because of miniaturization and sophistication of electronic products, required performances of semiconductor devices have become increasingly high and a new method for implementation of high-performance semiconductor devices, called “System in Package (SiP)”, has been developed. In this method, several LSI chips are densely-packed in one package. But heat flux in these devices is very high and sophisticated thermal management is necessary. The purpose of the present study is in situ evaluation of micro-scale thermal contact resistance in SiP-mounted devices. We have developed a measurement technique for micro-scale thermal contact resistance RT (RT range; 1×10-8 ~ 1×10-4 m2K/W) in SiP-mounted devices using Photothermal Reflectance Method. This method is a non-contact measurement method using a heating laser and a probing laser. A sample surface is periodically heated by a modulated laser beam, and the probing laser beam is irradiated at the same surface. Thermal contact resistance of the sample is measured by detecting the reflected laser beam and analyzing a phase-lag as a function of modulation frequency. The present study is focusing on a Flip-Chip junction structure which is a main route of heat removal in the device. The structure consists of several layers including an Au-bump and a Si-chip. To measure thermal contact resistance between an Au-bump and Si-chip, we applied a measurement apparatus using Photothermal Reflectance Method. We have measured Au-Si double-layered samples (20 × 20 mm2 square, the thickness of Au-layer; 30 μm and Si-layer; 300 μm) using this apparatus. We have analyzed a phase-lag using three-dimensional heat conduction model and detected a decrease of thermal contact resistance from 3.0×10-5 m2K/W to 3.8×10-7 m2K/W, due to junction between two contact surfaces. Furthermore, for analyzing measured phase-lag of the micro-scale sample configuration to detect thermal contact resistance, we improved three-dimensional heat conduction model with a micro-scale thickness and semi-infinite surface, and solved this model which reflects the micro-scale sample configuration (Au-bump; diameter is 70 μm, height is 30 μm and Si-Chip; thickness is 300 μm). We measured a phase-lag for Au-bump on Si-chip using Photothermal Reflectance Method and detected thermal contact resistance on the Flip-Chip junction structure using three-dimensional heat conduction model for micro-scale sample configuration.

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